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PT6965 LED Driver IC
DESCRIPTION
PT6965 is an LED Controller driven on a 1/5 to 1/8 duty factor. 11 segment output lines, 4 grid output lines, 3 segment/grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. Serial data is fed to PT6965 via a four-line serial interface. Housed in a 30-pin SSOP and TSSOP, PT6965 pin assignments and application circuit are optimized for easy PCB Layout and cost saving advantages.
FEATURES
* CMOS technology * Low power consumption * Multiple display modes (14 segment, 4 Grid to 11 segment, 7 Grid) * Key scanning (10 x 2 Matrix) * 8-Step dimming circuitry * Serial Interface for clock, data input, data output, strobe pins and low voltage operation ability when user's MCU power supply is 3.3 V * Available in 30-pin, SSOP and TSSOP
APPLICATIONS
* Micro-computer peripheral device * VCR set * Combo set
BLOCK DIAGRAM
Tel: 886-66296288Fax: 886-29174598 http://www.princeton.com.tw2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan
PT6965
APPLICATION CIRCUIT
Notes: 1. The capacitor (0.1 F) connected between the GND and the VDD pins must be located as close as possible to the PT6965 chip. 2. The PT6965 power supply is separate from the application system power supply. 3. 10 K R 1 K
COMMON CATHODE TYPE LED PANEL
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PT6965
ORDER INFORMATION
Valid Part Number PT6965-X PT6965-TX Package Type 30-pin, SSOP, 209mil 30-pin, TSSOP, 173mil Top Code PT6965-X PT6965-TX
PIN CONFIGURATION
OSC DOUT DIN CLK STB K1 K2 VDD SG1/KS1 SG2/KS2 SG3/KS3 SG4/KS4 SG5/KS5 SG6/KS6 SG7/KS7
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 30 29 28 27 26 25 24
GND GR1 GR2 GND GR3 GR4 GND VDD SG14/GR5 SG13/GR6 SG12/GR7 SG11 SG10/KS10 SG9/KS9 SG8/KS8
P T 69 6 5
23 22 21 20 19 18 17 16
PIN DESCRIPTION
Pin Name OSC I/O I Description Oscillator Input Pin A resistor is connected to this pin to determine the oscillation frequency Data Output Pin (N-Channel, Open-Drain) This pin outputs serial data at the falling edge of the shift clock. Data Input Pin This pin inputs serial data at the rising edge of the shift clock (starting from the lower bit) Clock Input Pin This pin reads serial data at the rising edge and outputs data at the falling edge. Serial Interface Strobe Pin The data input after the STB has fallen is processed as a command. When this pin is HIGH", CLK is ignored. Key Data Input Pins The data sent to these pins are latched at the end of the display cycle. (Internal Pull-Low Resistor) Power Supply Segment Output Pins (p-channel, open drain) Also acts as the Key Source Segment Output pins (P-Channel, open drain) Segment / Grid Output Pins Ground Pin Grid Output Pins Pin No. 1
DOUT
O
2
DIN CLK
I I
3 4
STB
I
5
K1, K2 VDD SG1/KS1 ~ SG10/KS10 SG11 SG12/GR7 ~ SG14/GR5 GND GR4 ~ GR1 V1.3
I O O O O
6, 7 8, 23 9 ~ 18 19 20 ~ 22 24, 27, 30 25, 26, 28, 29 3
PT6965
INPUT/OUTPUT CONFIGURATIONS
The schematic diagrams of the input and output circuits of the logic section are shown below. Input Pins: CLK, STB & DIN Output Pins: K1 to K2
Output Pins: DOUT, GR1 to GR4
Output Pins: SG1 to SG11
Output Pins: SG14/GR5, SG13/GR6 and SG12/GR7
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PT6965
FUNCTION DESCRIPTION
COMMANDS
A command is the first byte (b0 to b7) inputted to PT6965 via the DIN Pin after STB Pin has changed from HIGH to LOW State. If for some reason the STB Pin is set to HIGH while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid.
COMMANDS 1: DISPLAY MODE SETTING COMMANDS
PT6965 provides 4 display mode settings as shown in the diagram below: As stated earlier a command is the first one byte (b0 to b7) transmitted to PT6965 via the DIN Pin when STB is LOW. However, for these commands, the bit 3 & bit 8 (b2 to b7) are given a value of 0. The Display Mode Setting Commands determine the number of segments and grids to be used (14 to 11 segments, 4 to 7 grids). A display command ON must be executed in order to resume display. If the same mode setting is selected, no command execution is take place, therefore, nothing happens. When Power is turned ON, the 7-grid, 11-segment modes is selected. MSB 0 0 0 0 0 0 b1 LSB b0
Display Mode Settings: 00: 4 digits, 14 segments 01: 5 digits, 13 segments 10: 6 digits, 12 segments 11: 7 digits, 11 segments
COMMANDS 2: DATA SETTING COMMANDS
The Data Setting Commands executes the Data Write or Data Read Modes for PT6965. The data Setting Command, the bits 5 and 6 (b4, b5) are given the value of 0, bit 7 (b6) is given the value of 1 while bit 8 (b7) is given the value of 0. Please refer to the diagram below. When power is turned ON, bit 4 to bit 1 (b3 to b0) are given the value of 0. MSB 0 1 0 0 b3 b2 b1 LSB b0
Data Write & Read Mode Settings: 00: Write Data to Display Mode 10: Read Key Data Address Increment Mode Settings (Display Mode): 0: Increment Address after Data has been written 1: Fixed Address Mode Settings: 0: Normal Operation Mode 1: Test Mode
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PT6965 PT6965 KEY MATRIX & KEY INPUT DATA STORAGE RAM
PT6965 Key Matrix consists of 10 x 2 array as shown below:
K1 K2
SG1/ KS1
Each data entered by each key is stored as follows and read by a READ Command, starting from the last significant bit. When the most significant bit of the data (b0) has been read, the least significant bit of the next data (b7) is read. K1.....................K2 SG1/KS1 SG3/KS3 SG5/KS5 SG7/KS7 SG9/KS9 b0......................b1
Note: b2, b5, b6 and b7 do not care.
x x x x x b2
K1.....................K2 SG2/KS2 SG4/KS4 SG6/KS6 SG8/KS8 SG10/KS10 b3......................b4
x x x x x b5
x x x x x b6......................b7
SG10/KS10
Reading Sequence
SG 2/K S2
SG8/KS8
SG3/ KS3
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SG5/KS5
SG6/ KS6
SG9/KS9
SG7/ KS7
SG 4/K S4
6
PT6965 COMMANDS 3: ADDRESS SETTING COMMANDS
Address Setting Commands are used to set the address of the display memory. The address is considered valid if it has a value of 00H to 0DH. If the address is set to 0EH or higher, the data is ignored until a valid address is set. When power is turned ON, the address is set at 00H. Please refer to the diagram below. MSB 1 1 0 0 b3 b2 b1 LSB b0 Address: 00H to 0DH
DISPLAY MODE AND RAM ADDRESS
Data transmitted from an external device to PT6965 via the serial interface are stored in the Display RAM and are assigned addresses. The RAM addresses of PT6965 are given below in 8 bits unit. SG1 SG4 00HL 02HL 04HL 06HL 08HL 0AHL 0CHL SG5 00HU 02HU 04HU 06HU 08HU 0AHU 0CHU SG8 SG9 SG12 01HL 03HL 05HL 07HL 09HL 0BHL 0DHL SG13 SG14 01HU 03HU 05HU 07HU 09HU 0BHU 0DHU DIG1 DIG2 DIG3 DIG4 DIG5 DIG6 DIG7
b0 xxHL Lower 4 bits
b3
b4 xxHU Higher 4 bits
b7
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PT6965 COMMAND 4: DISPLAY CONTROL COMMANDS
The Display Control Commands are used to turn ON or OFF a display. It also used to set the pulse width. Please refer to the diagram below. When the power is turned ON, a 1/16 pulse width is selected and the displayed is turned OFF (the key scanning is started). MSB 1 0 0 0 b3 b2 b1 LSB b0
Dimming Quantity Settings: 000: Pulse width = 1/16 001: Pulse width = 2/16 010: Pulse width = 4/16 011: Pulse width = 10/16 100: Pulse width = 11/16 101: Pulse width = 12/16 110: Pulse width = 13/16 111: Pulse width = 14/16 Display Settings: 0: Display Off (Key Scan Continues) 1: Display On
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PT6965
SCANNING AND DISPLAY TIMING
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PT6965
KEY SCAN TIMING
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PT6965
SERIAL COMMUNICATION FORMAT
The following diagram shows the PT6965 serial communication format. The DOUT Pin is an N-channel, open-drain output pin, therefore, it is highly recommended that an external pull-up resistor (1 K to 10 K) must be connected to DOUT.
where: twait (waiting time) 1 s It must be noted that when the data is read, the waiting time (twait) between the rising of the eighth clock that has set the command and the falling of the first clock that has read the data is greater or equal to 1 s.
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PT6965
SWITCHING CHARACTERISTIC WAVEFORM
PT6961 Switching Characteristics Waveform is given below.
fosc OSC
50 %
PW ST B ST B PW CL K CLK tsetu p DIN tPZL DOUT tTZL Gn
90 % 10 % 90 %
PW CL K
tCL K -ST B
thold
tPLZ
tTLZ
90 % 10 % 90 % 10 %
Sn
10 %
tTZH
tTHZ
where: PWCLK (Clock Pulse Width) 400 ns tsetup (Data Setup Time) 100 ns tCLK-STB (Clock - Strobe Time) 1 s tTZH (Rise Time) 1 s fosc = Oscillation Frequency tTZL 1 s (VDD = 5 V) tTZL 2 s (VDD = 3 V) tTLZ 10 s (VDD = 5 V)
Note: Test Condition Under tTHZ (Pull low resistor = 10 K, Loading capacitor = 300 pF tTLZ (Pull high resistor = 10 K, Loading capacitor = 300 pF
PWSTB (Strobe Pulse Width) 1 s thold (Data Hold Time) 100 ns tTHZ (Fall Time) 10 s tPZL (Propagation Delay Time) 100 ns (5 V) tPZL (Propagation Delay Time) 200 ns (3 V) tPLZ (Propagation Delay Time) 300 ns (5 V) tPLZ (Propagation Delay Time) 600 ns (3 V) tTLZ 20 s (VDD = 3 V)
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PT6965
APPLICATIONS
Display memory is updated by incrementing addresses. Please refer to the following diagram.
The following diagram shows the waveforms when updating specific addresses.
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PT6965
RECOMMENDED SOFTWARE FLOWCHART
Notes: 1. Command 1: Display Mode Commands 2. Command 2: Data Setting Commands 3. Command 3: Address Setting Commands 4. Command 4: Display Control Commands 5. When IC power is applied for the first time, the content of the Display RAM is not defined; thus, it is strongly suggested that the contents of the Display RAM be cleared during the initial setting.
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PT6965
SSOP 30 (300MIL) THERMAL PERFORMANCE IN STILL AIR
JUNCTION TEMPERATURE: 100
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PT6965
ABSOLUTE MAXIMUM RATINGS
(Unless otherwise stated, Ta = 25 , GND = 0 V) Parameter Supply voltage Logic input voltage Driver output current Maximum driver output current/total Operating temperature Storage temperature Symbol VDD VI IOLGR IOHSG ITOTAL Topr Tstg Ratings -0.5 to +7 -0.5 to VDD+0.5 +250 -50 400 -40 ~ +85 -65 ~ +150 Unit V V mA mA mA
RECOMMENDED OPERATING RANGE
(Unless otherwise stated, Topr = -40 ~ +85 , GND = 0 V) Parameter Symbol Min. Logic supply voltage VDD 3 Dynamic Current (see Note1) IDDdyn High-level input voltage VIH 2.4 Low-level input voltage VIL 0 Typ. 5 Max. 5.5 5 VDD 1 Unit V mA V V
Note: 1. Test Condition: Set Display Control Commands = 80 H (Display Turn OFF State & under no load).
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PT6965
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD = 5 V, GND = 0 V, Ta = 25 ) Parameter Symbol Test Condition VO = VDD -2 V IOHSG(1) SG1 to SG11, SG12/GR7 High-level output current VO = VDD -3 V IOHSG(2) SG1 to SG11, SG12/GR7 VO = 0.3 V Low-level output current IOLGR GR1 to GR6, SG12/GR7 Low-level output current IOLDOUT VO = 0.4V VO = VDD -3 V Segment high-level ITOLSG SG1 to SG11, SG12/GR7 output current tolerance High-level input voltage VIH Low-level input voltage VIL Oscillation frequency K1 to K2 pull down resistor fosc RKN R = 51 K K1 to K2 VDD = 5 V Min. -20 -25 100 4 2.4 0 350 40 Typ. -25 -30 140 500 Max. -40 -50 5 3.3/VDD 0.8 650 100 Unit mA mA mA mA % V V KHz K
ELECTRICAL CHARACTERISTICS
(Unless otherwise stated, VDD = 3 V, GND = 0 V, Ta = 25 ) Parameter Symbol Test Condition VO = VDD -2V High-level output current IOHSG SG1 to SG11, SG12/GR7 VO = 0.3 V Low-level output current IOLGR GR1 to GR6, SG12/GR7 Low-level output current IOLDOUT VO = 0.4 V Segment high-level VO = VDD -2 V ITOLSG output current tolerance SG1 to SG11, SG12/GR7 High-level input voltage VIH Low-level input voltage VIL Oscillation frequency K1 to K2 pull down resistor fosc RKN R = 33 K K1 to K2 VDD = 3 V Min. -9 80 2 0.8VDD 0 350 90 Typ. -12 100 500 Max. -20 5 VDD 0.3 650 180 Unit mA mA mA % V V KHz K
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PT6965
PACKAGE INFORMATION
30 PINS, SSOP, 209 MIL
Symbol A A1 A2 b c e D E E1 L L1 R1
Notes: 1. All dimensions are in MILLMETERS. 2. Refer to JEDEC MO-150 AJ.
Min. 0.05 1.65 0.22 0.09 9.90 7.40 5.00 0.55 0.09 0
Nom. 1.75 0.30 0.15 0.65 BSC 10.20 7.80 5.30 0.75 1.25 REF 4
Max. 2.0 1.85 0.38 0.25 10.50 8.20 5.60 0.95 8
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PT6965
30PINS, TSSOP, 173MIL
Symbol A A1 b c e D E E1 L
Notes: 1. All dimensions are in MILLMETERS. 2. Refer to JEDEC MO-153 BC-1.
Min. 0.05 0.15 0.09 7.70 4.20 0.55 0
Nom. 0.20 0.50 BSC 7.80 6.40 BSC 4.40 0.75 4
Max. 1.20 0.25 0.20 8.15 4.60 0.95 8
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PT6965 IMPORTANT NOTICE
Princeton Technology Corporation (PTC) reserves the right to make corrections, modifications, enhancements, improvements, and other changes to its products and to discontinue any product without notice at any time. PTC cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a PTC product. No circuit patent licenses are implied. Princeton Technology Corp. 2F, 233-1, Baociao Road, Sindian, Taipei 23145, Taiwan Tel: 886-2-66296288 Fax: 886-2-29174598 http://www.princeton.com.tw
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